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Title: Advanced Methods for Chip Finishing in Large Nanometer Designs
Url: http://www.mentor.com/products/ic_nanometer_design/
Publisher: Mentor Graphics (Firm)
Description: This site from Mentor Graphics includes various resources on nanometer design. Nanometer designs have not only grown in density and function, but also in data volume; a single systems-on-chip (SoC) design can produce a file size larger than 12 gigabytes. Although large designs allow greater functionality and performance for the end user, for the designer they can be unmanageable. During the important full chip verification and chip finishing stage, a 12-gigabyte design can take hours to open for viewing and editing. Since there are generally several iterations done during this chip finishing stage, this not only forces down time- unproductive hours- but can also greatly affect a project schedule, especially at the time-sensitive back end when the project deadline is near. Yet it is in the design chip finishing stage that several important tasks must be completed before tape-out. These tasks include merging, creating, verifying and comparing various forms of the design data. Flows may vary from company to company, but the majority of the long list of individual tasks are consistent and are completed prior to mask creation. However, without an efficient and capable viewing and editing tool that can handle large designs, these tasks become extremely burdensome and time consuming if not impossible. Many viewing and editing tools areunable to complete the process in a reasonable amount of time, if at all. Designers are in urgent need of a solution that has the capability to open multi-gigabyte designs in a fast and efficient manner as well as allow editing and chip finishing tasks in a manner that is customizable and integrates into the designer's flow. Such a solution would allow design teams to continue developing designs with increased functionality without longer turn around times. It would also enable them to do more work in a shorter amount of time, reducing back-end pressures as deadlines draw near.This paper presents a case study of one semiconductor company's efforts to address the problem. It suggests current tools that address many chip finishing needs, and provides an example of a chip-finishing methodology that designers can easily integrate into their own design tool flowsusing CalibreĀ® DESIGNrev.
LC Classification: Technology -- Engineering (General). Civil engineering -- Engineering (General). Civil engineering (General) -- Engineering as a profession. Engineers
Technology -- Engineering (General). Civil engineering -- Engineering (General). Civil engineering (General) -- Materials of engineering and construction -- Materials of special composition or structure, A-Z -- Nanostructured materials
Technology -- Technology (General) -- Nanotechnology
GEM Subject: Science -- Engineering
Science -- Technology
Science -- Physics
Science -- Instructional issues
Vocational Education -- Technology
Key Concept: Manufacturing -- Nanofabrication
Resource Type: Instructional Materials
Reading Materials
Science Materials
Format: html
Audience: College/University Instructors
Higher Education
Professional Formation
Technical School First Cycle
Technical School Second Cycle
University First Cycle
University Postgrad
University Second Cycle
Vocational Training
Language: English
Rights: Mentor Graphics
Access Rights: Free access
Subject: Engineering Education
Materials Science and Engineering -- Advanced Instrumentation
Date Of Record Release: 2010-05-25 03:00:02 (W3C-DTF)
Date Last Modified: 2011-08-25 16:53:52 (W3C-DTF)
Source Type: ATE Center
Source: NetWorks
Full Record Views: 70
Resource URL Clicks: 16
Cumulative Rating: NOT YET RATED
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